Product Summary

The MT46V16M16BG-6IT:F is a double data rate SDRAM. It meets or surpasses all DDR266 timing requirements thus assuring full backwards compatibility with current DDR designs. In addition, the MT46V16M16BG-6IT:F supports concurrent auto-precharge and tRAS lockout for improved timing performance. The MT46V16M16BG-6IT:F will support an (tREFI) average periodic refresh interval of 7.8μs.

Parametrics

MT46V16M16BG-6IT:F absolute maxing ratings: (1)Delta Input/Output Capacitance: DQs, DQS, DM (for x4 or x8 devices) DCIO: max=0.50pF; DQ0-DQ7, LDQS, LDM (for lower byte of x16 devices), DCIO: max=0.50pF; DQ8-DQ15, UDQS, UDM (for upper byte of x16 devices) DCIO: max=0.50pF ; (2)Delta Input Capacitance: Command and Address DCI1: max=0.50pF ; (3)Delta Input Capacitance: CK, CK# DCI2: max=0.25pF ; (4)Input/Output Capacitance: DQs, DQS, DM (LDQS, LDM, UDM) CIO: min=3.50pF, max=4.00pF ; (5)Input Capacitance: Command and Address CI1: min=1.50pF, max=2.50pF ; (6)Input Capacitance: CK, CK# CI2: min=1.50pF, max=2.50pF ; (7)Input Capacitance: CKE CI3: min=1.50pF, max=2.50pF.

Features

MT46V16M16BG-6IT:F features: (1)167 MHz Clock, 333 Mb/s/p data rate; (2)VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V; (3)Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (×16 has two - one per byte); (4)Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle; (5)Differential clock inputs (CK and CK#); (6)Commands entered on each positive CK edge; (7)DQS edge-aligned with data for READs; centeraligned with data for WRITEs; (8)DLL to align DQ and DQS transitions with CK; (9)Four internal banks for concurrent operation; (10)Data mask (DM) for masking write data (×16 has two - one per byte).

Diagrams

MT46V16M16BG-6IT:F block diagram

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