(China (Mainland))
Product Summary
The GAL16V8D-15LJ is a High Performance E2CMOS PLD Generic Array, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<100ms) allow the High Performance E2CMOS PLD Generic Array Logic to be reprogrammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL16V8D-15LJ are the PAL architectures listed in the table of the macrocell description section. The GAL16V8D-15LJ is capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility.
Parametrics
GAL16V8D-15LJ absolute maximum ratings: (1)Supply voltage VCC: –0.5 to +7V; (2)Input voltage applied: –2.5 to VCC +1.0V; (3)Off-state output voltage applied: –2.5 to VCC +1.0V; (4)Storage Temperature: –65 to 150℃; (5)Ambient Temperature with Power Applied: –55 to 125℃.
Features
GAL16V8D-15LJ features: (1)high performance e2cmos® technology; (2)50% to 75% reduction in power from bipolar; (3)active pull-ups on all pins; (4)e2 cell technology; (5)eight output logic macrocells; (6)preload and power-on reset of all registers; (7)applications include; (8)electronic signature for identification.
Diagrams
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 GAL16V8D-15LJ |
Lattice |
SPLD - Simple Programmable Logic Devices 5V 16 I/O |
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GAL16V8D-15LJI |
Lattice |
SPLD - Simple Programmable Logic Devices 16 INPUT 8 OUTPUT 5V LOW POWER 15ns |
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GAL16V8D-15LJNI |
Lattice |
SPLD - Simple Programmable Logic Devices 16 INPUT 8 OUTPUT 5V LOW POWER 15ns |
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GAL16V8D-15LJN |
Lattice |
SPLD - Simple Programmable Logic Devices 16 Input 8 Output 5V Low Power 15ns |
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